The PDP-2 Instruction Register

Bus and State machine

   PDP-2 CPU Instruction Register discription

   The Instruction Register consists of an eight bit latch holding the
   op-code, Immediate data and Indirect bits. The address is held in
   a 16 bit loadable up counter, this allows the target address of the
   jsr instruction to be changed to M[MA+1], this is also used as the
   cycle counter for shift and rotate instructions. The split register
   load signals allow the IR to be updated with an indirect address.


   The IR control signals:
       IR-ADV advances the IR by one.
       IR-LOP loads the IR with the data on the upper 8 bits of the M-BUS
       IR-LAD loads the IR with the data on the lower 16 bits of the M-BUS
       IR-OAB enables the IR counter tri-state drivers feeding the A-BUS


   The register state for the PDP-2 is:

   AC<0:23>  accumulator
   MQ<0:23>  accumulator extension
   O         overflow flag
   C	     carry flag
   N	     neg flag
   Z	     zero flag
   PC<0:15>  program counter
?? PF<1:6>   program flags
   SW<0:23>  switch register

   A-BUS
   A-ADR = <0:15>
   A-SRC = <idle,PC,IR>	selecting PC or IR implies dest. of MAR

   M-BUS
   M-DAT = <0:23>
   M-SRC = <idle,MDR,MDR-EXT,PC,AC,IO,SW>
   M-DES = <idle,MDR,IR,PC,AC,IO>