The PDP-2 processor
Digital originally published plans to market PDP processors with word lengths of 18, 24, 30 and 36 bits(1). The PDP-2 designation was saved for a 24 bit processor that was never built. As far as is known no in depth design work was ever done for the PDP-2.

Now enter an alternate reality were the PDP-2 exists. 



A 1962 Digital publication(2) reported:


  Two new products, the PDP-2 and PDP-3, were proposed while the PDP-1 was
  in production. The PDP-2 never progressed beyond the initial stages. The
  PDP-3, a 36-bit computer based on PDP-1 concepts was designed but not
  built by the company.
We will likely never know what the 1960 PDP-2 would have looked like, but I imagine it might have taken the form of a 'stretch' PDP-1. With the experience of bringing the PDP-1 to market and Gordon Bell having not yet fully conceived the idea of auto-incrementing memory registers, the PDP-2 order code may have added or dropped a few instructions based on experience gained from programming the PDP-1, and optimized the logic design by encoding the order codes in ways that would simplify the implementation, but, otherwise followed the proven PDP-1 design rather closely. Another possible design direction might have been to augment the new design by the addition of one or more index registers, however the high cost of logic at that time could have made this addition prohibitively expensive. The result might likely have been a processor with a five or six bit order code, an indirect bit, possibly one or two index select bits and a large (15 to 17 bit) address space, eliminating the need for memory bank switching. The much larger word size would also made the addition of an 'immediate data' addressing mode a low cost way to reduce instruction counts (program size) and improve performance.

With these thoughts in mind I set out to design the PDP-2, and hopefully build one for myself. I have decided not to build the PDP-2 using a gate array, I wanted to actualy build something with parts I could touch and end up with a computer at least the size of a bread box, so I will be using 7400 series TTL (though, I may break down and sneak in a few PLD for the control logic state machine). One of the first realities you run into with 7400 series devices is that multiples of three or six and TTL (with very few exceptions) just don't run in the same pack. With this in mind I selected a basic memory referance instruction format consisting of a six bit op code, an immediate data bit, an indirect bit, and sixteen bits for a direct memory referance or immediate data. The immediate data format treats the indirect bit as the sign for the sixteen bit address field and extends it into the upper eight bits of the data word. This instruction format allows hardware selections of 3x8 or 6x4, very TTL friendly.

I am also planing a few changes to the order code list, the first major change is a totaly different jsp instruction and the dropping of the cal & jda instructions. The PDP-1 jda saves the accumulator at the call address and loads the current PC and overflow flag into the accumulator then transfers control to the instruction following the call address. This form always requires a dap to store the return address, precludes passing a single argument to a routine in the AC and requires an otherwise unneeded data path between the AC and the PC. The PDP-1 jsp is much like the jda, but does not save the AC, the cal is just strange, I'll leave it at that. The PDP-2 jsp saves the current PC in the call address then transfers control to the instruction following the call address, return is by an indirect jmp through the saved address, making the call/return shorter by one instruction and faster by one major cycle. I suspect that the reasion that this was not actualy done back in the day, is that it requires a hold register for the old PC so that it may be deposited at the call address, and a buss interconnect and gate cost much less that a latch.


(1) Datamation November/December 1959, vol. 5, no. 6, p. 24.
(2) Digital 1957 to Present, a Digital Equipment Corporation publication, 1978, p. 3.


PDP-2 CPU description 

   The register state for the PDP-2 is:

   IR<0:23>  instruction register   CPU state machine
   AC<0:23>  accumulator
   MQ<0:23>  MQ register
   OV        overflow flag
   PC<0:15>  program counter
   PF<1:6>   program flags
   SW<0:23>  switch register


   MAB                                  MDB
    |     |------------------------|     |
    |---->| Memory Address Reg     |     |
    |     |                        |     |
    |     |  Memory Data Reg       |     |
    |     |   & Data Sign Extend   |<--->|
    |     |------------------------|     |
    |                                    |
    |                                    |
    |     |------------------------|     |
    |<----| Program Counter        |---->|
    |     |------------------------|     |
    |                 ^                  |
    |                 |                  |
    |     |------------------------|     |
    |<----| Instruction Register   |<----|
    |     |------------------------|     |
    |                                    |
    |                                    |
    |     |------------------------|     |
    |     | Accumulator            |<--->|
    |     |------------------------|     |
    |                                    |
    |                                    |
    |     |------------------------|     |
    |     | Input/Output Register  |<--->|
    |     |------------------------|     |
    |                                    |
    |                                    |
    |     |------------------------|     |
    |<----| Switch Register        |---->|
    |     |------------------------|     |
    |                                    |
    |                                    |
    |     |------------------------|     |
    |---->| Bus Display            |<----|
          |------------------------|     |
                                         |
                                         |
          |------------------------|     |
          | I/O Devices            |<--->|
          |------------------------|

   The target major cycle time will be 500ns.


   The PDP-2 has five instruction formats:
      memory reference, shifts, skips, I/O transfer, and operate.
Memory reference instructions can access an address space of 64K words, or provide a sign extended 16 bit immediate data word (+/- 65536). When sign extending the Indirect Bit (ib) provides the sign. Indirection is limited to one level. 
   The memory reference format is:
     0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
   +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
   |       op        |id|ib|              address                          |
   +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
                       |  |
                       |  +------- Indirect bit
                       +---------- Immediate data <7:23> are sign extended

  op   mnemonic		action             major cycles
 <0:5>
  06	AND       AC = AC & ARG[]		1*	ALU logical AND
  05	IOR       AC = AC | ARG[]		1*	ALU logical OR
  04	XOR       AC = AC ^ ARG[]		1*	ALU logical XOR
  03	ADD       AC = AC + ARG[]		1*	ALU arithmetic
  02	SUB       AC = AC - ARG[]		1*	ALU arithmetic
  01    SUR	  AC = ARG[] - AC		1*	ALU arithmetic

  10	LAC       AC = ARG[]			1*	ALU logical 
  11	LMQ       MQ = ARG[]			1*

  12    MIA       AC = MQ                       1
  13    MAI       MQ = AC                       1

  14	INC       AC = M[MA] = M[MA]+1		3**
  15	DEC       AC = M[MA] = M[MA]-1		3**

  16	CMP       AC - ARG[] Set CC only	1*	ALU / arithmetic

  34	JMP       PC = [MA] 			1**

  36	MUS	  Multiply Step ARG[]		2*	ALU arithmetic / Shift
  37	DIS	  Divide Step ARG[]		2*	ALU arithmetic / Shift

  20	DAC       M[MA] = AC			2**	M-SRC=AC, M-DES=MDR
  21	DAP       M[MA]<8:23> = AC<8:23>	2**	M-SRC=AC, M-DES=MDR.A
  22	DIP       M[MA]<0:7> = AC<0:7>		2**	M-SRC=AC, M-DES=MDR.I
  23	DMQ       M[MA] = MQ 			2**	M-SRC=MQ, M-DES=MDR
  24	DZM       M[MA] = 0			2**	M-SRC=idle, M-DES=MDR
  25	JSP	  M[MA] = PC, PC = MA+1		3??	M-SRC=PC, M-DES=MDR

  xx	XEQ       M[MA] is executed as an instruction


  * Timing for Immediate argument, add one cycle for direct, two for indirect.
 ** Timing for direct address, add one cycle for indirect.
  # JMP provides three addressing modes:

   ARG[] = either M[MA] or bits <7:23> of the instruction sign extended
   MA = memory address (after indirection, if any)
Shift Group - sft (Operation Code 70) instructions will rotate or shift the Accumulator and/or the In-Out Register. When the two registers operate combined, the In-Out Register is considered to be a 24-bit magnitude extension of the right end of the Accumulator. Rotate is a non-arithmetic cyclic shift. That is the two ends of the register are logically tied together and information is rotated as though the reigster were a ring. Shift is an arithmetic operation and is, in effect, multiplication of the number in the register by 2N, where N is the number of shifts; plus is left and minus is right. As bits are shifted out from one end of a register they are replaced at the other end by ones if the number negative and zeroes if the number is positive. The sign bit is not shifted. The number of shift or rotate steps to be performed (N:1-15) is indicated by the one's complement shift count in instructions bits 20..23 
   The shift group format is:
     0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
   +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
   | 1  1  subopcode |                                         | shift cnt |
   +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
           |  |  |  |
           |  |  |  +-- 1 AC
           |  |  +----- 1 IO
           |  +-------- 0 rotate, 1 shift
           +----------- 0 left, 1 right

Rotate Acumulator Right
rar N Operation Code 71, SubOpCode 11
Rotates the bits of the Accumulator right N positions.

Rotate Acumulator Left
ral N Operation Code 61, SubOpCode 01
Rotates the bits of the Accumulator left N positions. 

Shift Acumulator Right
sar N Operation Code 75, SubOpCode 15
Shifts the contents of the Accumulator Right N positions.

Shift Acumulator Left
sal N Operation Code 65, SubOpCode 05
Shifts the contents of the Accumulator left N positions.

Rotate In-Out Register Right
rir N Operation Code 72, SubOpCode 12
Rotates the bits of the In-Out Register right N positions.

Rotate In-Out Register Left
ril N Operation Code 62, SubOpCode 02
Rotates the bits of the In-Out Register left N positions.

Shift In-Out Register Right
sir N Operation Code 76, SubOpCode 16
Shifts the contents of the In-Out Register right N positions

Shift In-Out Register Left
sil N Operation Code 66, SubOpCode 06
Shifts the contents of the In-Out Register left N positions.

Rotate AC and IO Right
rcr N Operation Code 73, SubOpCode 13
Rotates the bits of the combined registers right in a single ring N positions

Rotate AC and IO Left
rcl N Operation Code 63, SubOpCode 03
Rotates the bits of the combined registers left in a single ring N positions

Shift AC and IO Right
scr N Operation Code 77, SubOpCode 17
Shifts the contents of the combined registers right N positions

Shift AC and IO Left
scl N Operation Code 67, SubOpCode 07
Shifts the contents of the combined registers left N positions




   The skip format is:

     0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
   +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
   | 1  1  0  1  0  X                              | 0  1  2  3  4  5  6  7|
   +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
                             |  |  |  |  |  |  |  | \______________________/
		             |  |  |  |  |  |  |  |	       |      
	                     |  |  |  |  |  |  |  |         sense sw
                             |  |  |  |  |  |  |  +-------- AC == 0
	                     |  |  |  |  |  |  +----------- AC >= 0
		             |  |  |  |  |  +-------------- AC < 0
		             |  |  |  |  +----------------- OV == 0
		             |  |  |  +-------------------- IO >= 0
                             |       
                             |       
	                     +----------------------------------- invert skip



   A-BUS
   A-ADR = <0:15>
   A-SRC = <idle,PC,IR>	selecting PC or IR implies dest. of MAR

   M-BUS
   M-DAT = <0:23>
   M-SRC = <idle,MDR,MDR-EXT,PC,AC,MQ,SW>
   M-DES = <idle,MDR,IR,PC,AC,MQ>


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